Dunno if we can have 2 memory partitions on memory banks limits: One for the GPU and one for the CPU, namely until the CPU<->GPU are working on their own partition of the memory, the memory controller could issue commands for separated sets of memory banks in parallel (could CLX 3.0 handle that)?
Basically, it would mean a iGPU close to the speed of a dGPU. No DMA engine, no PCIe.
Dunno if we can have 2 memory partitions on memory banks limits: One for the GPU and one for the CPU, namely until the CPU<->GPU are working on their own partition of the memory, the memory controller could issue commands for separated sets of memory banks in parallel (could CLX 3.0 handle that)?
Basically, it would mean a iGPU close to the speed of a dGPU. No DMA engine, no PCIe.